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d a t a sh eet preliminary speci?cation supersedes data of 1995 oct 11 file under integrated circuits, ic12 1997 apr 01 integrated circuits pcb2421 1k dual mode serial eeprom
1997 apr 01 2 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning 6 functional description 6.1 transmit-only mode (ddc1) 6.2 initialization procedure 6.3 bidirectional mode (ddc2b, i 2 c-bus mode) 6.3.1 bidirectional mode bus characteristics 6.3.2 bus not busy (a) 6.3.3 start condition (b) 6.3.4 stop condition (c) 6.3.5 data valid (d) 6.3.6 acknowledge 6.3.7 slave address 6.4 write operation 6.4.1 byte write 6.4.2 page write 6.5 acknowledge polling 6.6 write protection 6.7 read operation 6.7.1 current address read 6.7.2 random read 6.7.3 sequential read 6.8 pin description 6.8.1 sda 6.8.2 scl 6.8.3 vclk 6.8.4 wp 6.8.5 test 6.8.6 n.c. 7 limiting values 8 dc characteristics 9 eeprom characteristics 10 ac characteristics 11 application information 11.1 diode protection 11.2 functional compatibility with microchip 24cl21 dual mode eeprom 12 package outlines 13 soldering 13.1 introduction 13.2 dip 13.2.1 soldering by dipping or by wave 13.2.2 repairing soldered joints 13.3 so 13.3.1 reflow soldering 13.3.2 wave soldering 13.3.3 repairing soldered joints 14 definitions 15 life support applications 16 purchase of philips i 2 c components
1997 apr 01 3 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 1 features single supply with operation 4.5 to 5.5 v completely implements ddc1/ddc2b interface for monitor identification low power cmos technology two-wire i 2 c-bus interface self-timed write cycle (including auto-erase) page-write buffer for up to 8 bytes write-protect pin 100 khz i 2 c-bus compatibility designed for 10000 erase/write cycles minimum data retention greater than 10 years 8-pin dip and so package temperature range 0 to +70 c. 2 general description the philips pcb2421 is a 128 8-bit dual mode serial electrically erasable prom (eeprom). this device is designed for use in applications requiring storage and serial transmission of configuration and control information. two modes of operation have been implemented: transmit-only mode (ddc1 mode) and bidirectional mode (ddc2b, or i 2 c-bus mode). upon power-up, the device will be in the transmit-only mode, sending a serial bitstream of the entire memory array contents, clocked by the vclk pin. a valid high-to-low transition on the scl pin will cause the device to enter the bidirectional mode, with byte selectable read/write capability of the memory array. the pcb2421 is available in a standard 8-pin dual in-line and 8-pin small outline package operating in a commercial temperature range. 3 ordering information type number package name description version PCB2421P dip8 plastic dual in-line package; 8 leads (300 mil) sot97-1 pcb2421t so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1
1997 apr 01 4 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 4 block diagram fig.1 block diagram. (1) factory use only. bo ok, full pagewidth mbg271 i/o control logic 5 sda scl vclk wp memory control logic x decoder hv generator page latches eeprom array y decoder sense amplifier r/w control pcb2421 n.c. test (1) 3 6 7 1 2 48 v ss v dd 5 pinning symbol pin description test 1 factory use only: must be tied to v dd ; may not be left open-circuit n.c. 2 may be tied to v ss , v dd , or left open-circuit wp 3 write protect input (low = write protected, high = not write protected); may not be left open-circuit v ss 4 ground sda 5 serial data input/output scl 6 serial clock input/output (ddc2b) vclk 7 serial clock input (transmit-only mode, ddc1) v dd 8 supply voltage fig.2 pin configuration. handbook, halfpage 1 2 3 4 8 7 6 5 mbg272 pcb2421 test v dd n.c. vclk wp scl v ss sda
1997 apr 01 5 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 6 functional description the pcb2421 operates in two modes, the transmit-only mode (ddc1) and the bidirectional mode (ddc2, or i 2 c-bus mode). there is a separate two-wire protocol to support each mode, each having a separate clock input and sharing a common data line (sda). the device enters the transmit-only mode (ddc1) upon power-up. in this mode the device transmits data bits on the sda pin in response to a clock signal on the vclk pin. the device will remain in this mode until a valid high-to-low transition is placed on the scl input. when a valid transition on scl is recognized, the device will switch into the bidirectional mode (see fig.3). the only way to switch the device back to the transmit-only mode (ddc1) is to remove power from the device. 6.1 transmit-only mode (ddc1) the device will power-up in the transmit-only mode. this mode supports a unidirectional two-wire protocol for transmission of the contents of the memory array (see fig.12). the pcb2421 requires that it be initialized prior to valid data being sent in the transmit-only mode (see section initialization procedure, and fig.4). in this mode, data is transmitted on the sda pin in 8-bit bytes, each byte followed by a ninth clock pulse during which time sda is left high-impedance. the clock source for the transmit-only mode is provided on the vclk pin; a data bit is output on the rising edge on this pin. the 8 bits in each byte are transmitted most significant bit first. each byte within the memory array will be output in sequence. when the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. the bidirectional mode clock (scl) pin must be held high for the device to remain in the transmit-only mode. 6.2 initialization procedure at power-on, after v dd has stabilized, the device will be in the transmit-only mode. nine clock cycles on the vclk pin must be given to the device for it to perform internal synchronization. during this period, the sda pin will be in a high-impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. the device will power-up with address pointer at 00h (see fig.4). 6.3 bidirectional mode (ddc2b, i 2 c-bus mode) the pcb2421 can be switched into the bidirectional mode (see fig.3) by applying a valid high-to-low transition on the bidirectional mode clock (scl). when the device has been switched into the bidirectional mode, the vclk input is disregarded. this mode supports a two-wire bidirectional data transmission protocol (i 2 c-bus protocol). in the i 2 c-bus protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. the bus must be controlled by a master device that generates the bidirectional mode clock, controls access to the bus, and generates the start and stop conditions, while the pcb2421 acts as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 6.3.1 b idirectional mode bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (see fig.6). 6.3.2 b us not busy (a) both data (sda) and clock (scl) lines remain high. 6.3.3 s tart condition (b) a high-to-low transition of the sda line while scl is high determines a start condition. all commands must be preceded by a start condition. 6.3.4 s top condition (c) a low-to-high transition of the sda line while scl is high determines a stop condition. all operations must be ended with a stop condition. 6.3.5 d ata valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the maximum number of data bytes transferred between the start and stop conditions during a write operation is 8 bytes (see section page write and fig.5).
1997 apr 01 6 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 the maximum number of data bytes transferred between start and stop conditions during a read operation is unlimited. 6.3.6 a cknowledge the pcb2421, when addressed in ddc2b mode, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra (9th) clock pulse which is associated with this acknowledge bit. the pcb2421 does not generate an acknowledge if an internal programming cycle is in progress (sda line is left high during the 9th clock pulse). the pcb2421 generates an acknowledge by pulling down the sda line during the acknowledge pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must also be taken into account. the master receiver must signal an end of data to the pcb2421 by not generating an acknowledge bit on the last byte that has been clocked out of the slave transmitter. in this case, the slave transmitter pcb2421 must leave the data line high to enable the master to generate the stop condition. 6.3.7 s lave address after generating a start condition, the bus master transmits the slave address (msb first) consisting of a 7-bit device address (1010000) for the pcb2421. the eighth bit of the slave address determines if the master device wants to read or write to the pcb2421 (r/ w bit) (see fig.7). the pcb2421 monitors the bus for its corresponding slave address all the time. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. table 1 slave address 6.4 write operation 6.4.1 b yte write following the start condition from the master, the device address (7 bits), and the r/ w bit (logic low for write) is placed on the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore the next byte transmitted by the master is the word address operation slave address r/ w read 1010000 1 write 1010000 0 and will be written into the address pointer of the pcb2421. after receiving another acknowledge signal from the pcb2421, the master device will transmit the data word to be written into the addressed memory location. the pcb2421 acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the pcb2421 will not generate acknowledge signals. 6.4.2 p age write for a page write, the write control byte, word address, and the first data byte are transmitted to the pcb2421 in the same way as in a single byte write. but instead of generating a stop condition the master transmits up to eight data bytes to the pcb2421 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain constant. a maximum of 8 bytes can be written in one operation. as with the byte write operation, once the stop condition is received an internal write cycle will begin (see figs 5 and 8). 6.5 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. acknowledge (ack) polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/ w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see fig.9 for flow diagram. 6.6 write protection pin 3 is a write protect input ( wp). in the ddc1 mode, the pcb2421 can only be read according to the ddc1 protocol, hence the wp input has no effect in this mode. in the ddc2b mode, when wp is connected to ground, the entire eeprom is write-protected, regardless of other pin states. when connected to v dd , write-protection is disabled and the eeprom may be programmed. wp may not be left open-circuit.
1997 apr 01 7 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 table 2 mode con?gurations note 1. where x = dont care. 6.7 read operation read operations are initiated in the same way as write operations with the exception that the r/ w bit of the slave address is set to logic 1. there are three basic types of read operations: current address read, random read, and sequential read. 6.7.1 c urrent address read the pcb2421 contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w set to logic 1, the pcb2421 issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer but does generate a stop condition and the pcb2421 discontinues transmission (see fig.10). 6.7.2 r andom read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the pcb2421 as part of a normal write operation. after the word address is sent, the master generates a repeated start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again but with the r/w bit set to logic 1. the pcb2421 will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the pcb2421 discontinues transmission (see fig.11). 6.7.3 s equential read sequential reads are initiated in the same way as a random read except that after the pcb2421 transmits the first data byte, the master issues an acknowledge as ddc wp mode dcc1 x (1) r dcc2 1 r/w 0r opposed to a stop condition in a random read. this directs the pcb2421 to transmit the next sequentially addressed 8-bit word. to provide sequential reads the pcb2421 contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 6.8 pin description 6.8.1 sda this pin is used to transfer addresses and data into and out of the device, when the device is in the bidirectional (i 2 c-bus, ddc2b) mode. in the transmit-only mode (ddc1), which only allows data to be read from the device, data is also transferred on the sda pin. this pin is an open-drain terminal, therefore the sda bus requires a pull-up resistor connected to v dd (typically 10 k w for 100 khz). see brochure the i 2 c-bus and how to use it (order no. 9398 393 40011) or data handbook ic12 . 6.8.2 scl this pin is the clock input for the bidirectional mode (i 2 c-bus, ddc2b), and is used to synchronize data transfer to and from the device. it is also used as the signalling input to switch the device from the transmit-only mode to the bidirectional mode. it must remain high for the chip to continue operation in the transmit-only mode (ddc1). 6.8.3 vclk this pin is the clock input for the transmit-only mode (ddc1). in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in ddc2b mode, this input is a dont care. 6.8.4 wp this pin is used to inhibit writing of the eeprom. when this pin is connected to ground, writing of the eeprom is inhibited. when connected to v dd (and vclk = v dd ), the eeprom can be programmed. wp may not be left open-circuit. wp input is a dont care in ddc1 mode. 6.8.5 t est pins 1 is a test pin for factory use only. it must be connected to v dd in the application. 6.8.6 n . c . this pin has no connection and may be tied to v ss , v dd or left open-circuit.
1997 apr 01 8 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 fig.3 mode transition diagram. handbook, full pagewidth mbg275 sda vclk scl t vhz transmit only mode (ddc1) bidirectional mode (ddc2) fig.4 device initialization diagram. d book, full pagewidth mbg276 sda vclk scl high-impedance for 9 clock cycles v dd bit 8 bit 7 t vaa t vaa 11 10 9 8 12 t vpu
1997 apr 01 9 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 fig.5 example of writing 8 bytes with word address x0000000 and 6 bytes with word address x0010101. handbook, full pagewidth mbg277 0 x0000000 word address 1 2 3 4 5 6 7 8 1 x0001. . . 2 x0010101 4 56 row 3 x0011. . . column 0 1 2 3 4 5 6 7 1 2 3 x = dont care. fig.6 ddc2b data transfer sequence on the i 2 c-bus. handbook, full pagewidth mbg278 sda scl (a) (b) (d) (d) (c) stop condition data allowed to change data or acknowledge valid start condition
1997 apr 01 10 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 fig.7 slave address. handbook, halfpage mbg279 1010000r/w fig.8 i 2 c-bus write protocol (n = maximum 8 bytes). handbook, full pagewidth s 0ax slave address word address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave writing r/w don't care auto increment memory word address mbg280 n bytes t wr
1997 apr 01 11 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 handbook, halfpage mbg281 send stop condition to initiate write cycle send write command send start send control byte with r/w = 0 did device acknowledge (ack = 0)? no next operation yes fig.9 acknowledge polling. fig.10 current address read. handbook, full pagewidth mbg282 s p stop start sda no ack r/w ack data slave address + r/w
1997 apr 01 12 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 fig.11 random read. h andbook, full pagewidth mbg283 s s start data slave address + r/w p data rep start slave address + r/w stop sda r/w ack r/w ack no ack
1997 apr 01 13 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 7 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: equivalent to discharging a 100 pf capacitor through a 1.5 k w series resistor. 8 dc characteristics v dd = 4.5 to 5.5 v; v ss =0v; t amb =0to+70 c; unless otherwise speci?ed. 9 eeprom characteristics v dd = 4.5 to 5.5 v; v ss =0v; t amb =0to+70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage - 0.3 +7.0 v v n input voltage on any pin measured via 500 w resistor - 0.5 v dd(max) + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma p tot total power dissipation - 150 mw p o power dissipation per output - 50 mw t stg storage temperature without eeprom retention - 65 +150 c with eeprom retention - 65 +70 c t amb operating ambient temperature 0 +70 c v es electrostatic discharge note 1 - 2000 +2000 v symbol parameter conditions min. typ. max. unit v dd supply voltage 4.5 - 5.5 v v ih high level input voltage (pins 3, 5 and 6) 0.7v dd -- v v il low level input voltage (pins 3, 5 and 6) -- 0.3v dd v v ih(7) high level input voltage (pin 7) 2.0 -- v v il(7) low level input voltage (pin 7) -- 0.8 v v ol low level output voltage i ol = 3 ma; v dd = 4.5 v -- 0.4 v i li input leakage current v i = 0 to 5.5 v - 10 - +10 m a i lo output leakage current v o = 0 to 5.5 v - 10 - +10 m a i dd(write) operating write current f scl = 100 khz; v dd = 5.5 v -- 1000 m a i dd(read) operating read current f scl = 100 khz; v dd = 5.5 v -- 400 m a i dd(st) standby current v dd = 5.5 v; ddc2b mode; vclk = sda = scl = v dd -- 30 m a symbol parameter min. max. unit t wr eeprom write time - 20 ms n cyc eeprom endurance 10000 - e/w cycles t ret eeprom retention 10 - years
1997 apr 01 14 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 10 ac characteristics v dd = 4.5 to 5.5 v; v ss =0v; t amb =0to+70 c; unless otherwise speci?ed. notes 1. the rise time for sda returning high must be observed after this period. 2. this is the time that the bus must be free before a new transmission can start. symbol parameter conditions min. typ. max. unit ddc1 mode (transmit-only; unidirectional) t vaa output valid from vclk see fig.12; note 1 - 1 -m s t vhigh vclk high time see fig.12 20 --m s t vlow vclk low time see fig.12 20 --m s t vhz mode transition time see fig.3; note 1 - 500 - ns t sp input ?lter spike suppression time -- 100 ns t vpu ddc1 mode power-up time see fig.4 - 5 -m s ddc2b mode (bidirectional; i 2 c-bus mode); see fig.13 f scl serial clock frequency 0 - 100 khz t high serial clock high time 4 --m s t low serial clock low time 4.7 --m s t r scl and sda rise time -- 1 m s t f scl and sda fall time -- 0.3 m s t hd;sta start condition hold time 4 --m s t su;sta start condition set-up time 4.7 --m s t hd;dat data input hold time 0 --m s t su;dat data input set-up time 250 -- ns t su;sto stop condition set-up time 4 --m s t buf bus free time note 2 4.7 --m s t sp input ?lter spike suppression -- 100 ns
1997 apr 01 15 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 fig.12 transmit-only mode (ddc1). handbook, full pagewidth mbg273 sda vclk scl bit 1 (lsb) bit 8 (msb) bit 7 null bit t vaa t vhigh t vlow fig.13 ddc2b (i 2 c-bus timing). handbook, full pagewidth protocol scl sda mbg274 bit 0 lsb (r/w) t hd;sta t su;dat t hd;dat t su;sto t f r t t buf t su;sta t low t high 1 / f scl start condition (s) bit 7 msb (a7) bit 6 (a6) acknowledge (a) stop condition (p)
1997 apr 01 16 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 11 application information 11.1 diode protection there is no diode connection between vclk and v dd , scl and v dd and sda and v dd (see fig.14). this allows powering-down the device without affecting the i 2 c-bus operation or loading the vclk driver. 11.2 functional compatibility with microchip 24cl21 dual mode eeprom the philips pcb2421 is pin and function compatible with the 24cl21 providing the following measures are taken in the application. 1. pin 1 ( test) must be tied to v dd 2. pin 3 ( wp) must be tied to v dd . this inhibits the write protection function which does not exist on the 24cl21 at this time 3. maximum 100 khz ddc2b clock frequency 4. maximum 25 khz ddc1 vclk clock frequency 5. during eeprom programming a maximum write time of 20 ms must be observed 6. 8-byte maximum during page write must be observed 7. during operation v dd must be between 4.5 and 5.5 v 8. an operating temperature between 0 and +70 c must be observed 9. output valid from vclk (t vaa ) typical 1 m s must be observed 10. ddc1 mode power-up time (t vpu ) typical 5 m s should be observed. remark : vclk is dont care in the ddc2b mode. fig.14 pcb2421 diode protection. handbook, halfpage mbg284 scl sda wp n.c. v dd v ss vclk test 1 2 3 4 8 7 6 5 substrate pcb2421
1997 apr 01 17 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 12 package outlines references outline version european projection issue date iec jedec eiaj sot97-1 92-11-17 95-02-04 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.045 0.17 0.020 0.13 b 2 050g01 mo-001an m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
1997 apr 01 18 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03s ms-012aa 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 95-02-04 97-05-22
1997 apr 01 19 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 13 soldering 13.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 13.2 dip 13.2.1 s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 13.2.2 r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. 13.3 so 13.3.1 r eflow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 13.3.2 w ave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.3.3 r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 apr 01 20 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 14 definitions 15 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 16 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1997 apr 01 21 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 notes
1997 apr 01 22 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 notes
1997 apr 01 23 philips semiconductors preliminary speci?cation 1k dual mode serial eeprom pcb2421 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2870, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 417067/1200/02/pp24 date of release: 1997 apr 01 document order number: 9397 750 01746

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